1. Technical Field of the Invention
The present invention relates to a semiconductor device and test device for same.
2. Description of the Related Art
There is an increased demand for an increase in integration density in semiconductor devices reflecting the increase of the mount density and functions in the electronic appliances using such semiconductor devices.
The integration increase of semiconductor devices, in general, is achieved by scaling-down the circuit elements configuring such semiconductor devices. Namely, integration increase is done by micro-fabricating the interconnections, connection holes and the like configuring the circuit elements.
On the other hand, in order to reduce the cost and improve the yield of semiconductor devices, there is a need for a technology to increase the number of semiconductor chips formed on one wafer to the greatest possible extent. Namely, there is a necessity for a technology to optimize, for scale-down, the design and manufacturing process such that circuits used for the same function are realized within as small a chip as possible.
For a product group in the same generation realizing the same function, e.g. DRAM (Dynamic Random Access Memory), the design is under a comparatively relaxed condition of design rule in an early stage of placement into the market. Consequently, chip size is comparatively great and cost is somewhat high correspondingly.
However, in the middle or later stage of placement into the market, chip size is reduced as a result of scaling-down efforts. Thus, simultaneous achievement is made on cost reduction per chip and yield improvement.
Such chip-size reduction is made over several times on a product group in the same, generation. Furthermore, chip-size reduction is repeated from generation to generation. As a result, reduction is simultaneously done for the interconnect pattern on the chip surface. Due to this, reduction is natural on the size and pitch of the test pads for testing semiconductor devices.
In this manner, by the increase of test pads due to the increase of chip count per wafer, difficulties tend to arise in testing with the existing test method.
Under such a circumstance, as described in JP-A-11-27451, a testing method has been developed in which probes, beams, interconnections and secondary pads are formed on the same silicon substrate, as a testing substrate, as that of a semiconductor device so that the projecting probes respectively formed on the beams are contacted with a predetermined pad formed on the semiconductor device, thereby conducting a test.
Meanwhile, as described in JP-A-2000-227459, a BIST (Built-In Self Test) circuit has been incorporated on a semiconductor chip to enable a simplified test.
However, there is a further demand for the integration increase on the semiconductor device. Due to the increase of pad count and the reduction of arrangement area, further reduction is required for pad pitch. However, there is a fear of difficulty in fabricating a testing substrate for a test device capable of coping with the pad pitch reduction in the semiconductor devices.
Namely, although the semiconductor-device test device is formed with probes, beams, interconnections and secondary electrode pads on a silicon substrate thereof, as noted above, there is a need to narrow the width of the beam due to the pad pitch reduction in a probe semiconductor device. If the pad arrangement remains as in the conventional structure, problems of strength and difficulties in fabrication of the beams are correspondingly caused.
It is an object of the present invention to realize a semiconductor device in which testing is effectively possible by the test device even where the semiconductor device is reduced in chip size and hence pad pitch.